Integrated circuits are fabricated on wafers of a semiconductor substrate. After the integrated circuits have been fabricated on the wafer, they are “singulated,” i.e., separated from each other, to provide a plurality of semiconductor dies. Each semiconductor die is typically placed in a package having externally accessible terminals that are connected by bonding wires to respective bonding pads fabricated on the die.
Each integrated circuit package most commonly contains a single integrated circuit die. However, it is sometimes desirable to place two or more integrated circuit dies in a single package. For example, if the integrated circuit is a memory device, such as a flash memory device, the desired capacity of the memory device may exceed the currently available capacity of memory device dies. If, for example, a user desires a 16 GB flash memory device and the maximum available capacity of flash memory device dies is only 8 GB, a 16 GB flash memory device can be provided by placing two of the memory device dies in the package.
Multiple memory device dies may be packaged together using a variety of techniques. One common technique is to stack one or more of the dies on top of another, which is known as a “stacked die” configuration. However, in a stacked die configuration, only the top die is generally accessible for routing power and signals to and from the die. Signals generally cannot be routed directly to bonding pads on the lower die because the upper die covers the bonding pads on the lower die. Bonding pads could be made accessible on the lower die by fabricating the lower die in a configuration that spatially mirrors the configuration of the upper die, and by turning the lower die upside down so that its bonding pads face downwardly. However, this technique would require that two different versions of the die—an upper die configuration and a lower die configuration—be manufactured. Yet economic considerations make this approach undesirable. Also, this approach would not allow more than two dies to be stacked since the bonding pads on the middle die(s) would not be accessible.
The most common approach to stacking dies in a manner that solves the above problems is to fabricate extra bonding pads on the dies. The extra bonding pads on the upper die are connected to interconnects extending through the dies to pads formed on the lower surface of the dies. The bonding pads on the lower surface of the upper die are connected to respective bonding pads on the upper surface of the lower die to allow signals to be coupled to and from the lower die through the extra bonding pads fabricated on the upper die. For example, a data signal, such as data signal D0 for data bit 0 is applied to a bonding pad fabricated on the upper die, and it is also applied through the interconnect to the corresponding bonding pad fabricated on the lower die, which is located directly beneath the bonding pad on the upper die. The data signals can be applied to both dies in this manner because, in certain devices, such as memory devices, the signals are common to both dies. Other signals that may be common to multiple stacked memory device dies are address signals and clock signals. Ground and power will also generally be common to both dies. However, certain other signals are not common to both dies and must instead be individually applied to each die. For example, in the context of memory devices, separate chip select CS, clock enable CKE, and on die termination ODT signals must be individually applied to each die. Additionally, an impedance ZR pad fabricated on each die must be separately accessible.
Signals are typically applied separately to stacked die using the prior art approach shown in FIG. 1, it being understood that FIG. 1 shows only a few of the signals that are normally applied to stacked memory device dies. As shown in FIG. 1, an upper die 10 is stacked on an identical lower die 12. Upper surfaces 16 of each die 10, 12 have formed thereon respective pairs of bonding pads 20, 22 for signals that are common to both dies 10, 12. For example, the D0 signal may be received by and transmitted from the bonding pad 20, and a bit of an address signal A0 may be received by the bonding pad 22. The bonding pads 20, 22 are connected to a respective circuit 24 that is also fabricated on the upper surfaces 16 of each die 10, 12. With reference also to FIG. 2, the bonding pads 20, 22 are connected through respective interconnects 26, 28 extending through the dies 10, 12 and connected to respective pads 30, 32 fabricated on a lower surface 36 of each die 10, 12. Insofar as the pads 30, 32 are directly beneath the bonding pads 20, 22, respectively, the bonding pads 30, 32 of the upper die 10 can be positioned directly on top of the bonding pads 20, 22, respectively, on the upper surface 16 of the lower die 12. As a result, signals applied to and/or received from the bonding pads 20, 22 on the upper die 10 can be applied to and/or received from the bonding pads 20, 22 on the lower die 12.
As mentioned above, some signals must be individually applied to each of the die 10, 12. With further reference to FIG. 1, a chip select CS signal for the upper die 10 is applied to a bonding pad 40a, a clock enable CKE signal for the upper die 10 is applied to a bonding pad 42a, an on-die termination ODT signal for the upper die 10 is applied to a bonding pad 44a, and an impedance test node ZR for the upper die 10 is available through a bonding pad 46a, all of which are connected to the circuit 24 fabricated on the upper surface 16 of the respective dies 10, 12. However, extra bonding pads 40b, 42b, 44b, 46b corresponding to the bonding pads 40a, 42a, 44a, 46a, respectively, are also fabricated on the upper surface of each die 10, 12. These bonding pads 40b, 42b, 44b, 46b are for the CS, CKE and ODT signals and the ZR test node for the lower die 12. With further reference to FIG. 2, the bonding pads 40b, 42b, 44b, 46b are connected to respective interconnects 46, 47, 48, 49 extending through the dies 10, 12 to respective pads 50, 52, 54, 56 fabricated on a lower surface 36 of each of the dies 10, 12. This configuration allows the CS, CKE and ODT signals applied to the bonding pads 40b, 42b, 44b respectively, of the upper die 10 to be applied to the bonding pads 40b, 42b, 44b of the lower die 12, and the ZR test node accessible through the bonding pad 46b of the upper die 10 to be applied to the bonding pad 46b of the lower die 12. However, the bonding pads 40b, 42b, 44b, 46b cannot be connected to the circuits 24 fabricated on the dies 10, 12 or else the CS, CKE and ODT signals applied to the bonding pads 40b, 42b, 44b of the upper die 10 and the ZR test point of the upper die 10 would be coupled to the circuits 24 fabricated on both dies 10, 12. This problem could be solved by fabricating a lower die 12 with a different topography from the upper die 10, e.g., coupling the circuit 24 of the lower die 12 to the bonding pads 40b, 42b rather than to the bonding pads 40a, 42a. However, as mentioned above, for economic reasons, it is generally desirable to make both die 10, 12 identical to each other.
The above-described problem is generally solved by positioning an insulative redistribution layer 60 between the lower surface 36 of the upper die 10 and the upper surface 16 of the lower die 12. The redistribution layer 60 has pads 62, 64, 66, 68 fabricated on an upper surface 69 of the redistribution layer 60 that are in alignment with, and in contact with, the pads 50, 52, 54, 56 respectively, fabricated on a lower surface 36 of the upper die 10. The pads 62, 64, 66, 68 are coupled through respective conductors 70, 72, 74, 76 to pads 80, 82, 84, 86 respectively, fabricated on a lower surface 88 of the redistribution layer 60. The pads 80, 82, 84, 86 are in alignment with, and in contact with, the bonding pads 40a, 42b, 44b, 46b, respectively, fabricated on a upper surface 36 of the lower die 12. As a result, the CS, CKE, ODT and ZR bonding pads 40b, 42b, 44b, 46b of the upper die 10 are coupled to the bonding pads 40a, 42a, 44b, 46b of the lower die 12, which are coupled to the circuit 24 fabricated on the lower die 12.
The use of the redistribution layer 60, while necessary, produces some undesired consequences. There is not only the expense of fabricating the redistribution layer 60 and the expense of assembling it with the dies 10, 12, but it also creates signal paths for the signals applied to the upper die 10 that can be significantly longer than the signal paths for the signals applied to the lower die 12. For example, the path lengths of the CS, CKE and ODT signals applied to the lower die 12 are increased by the distances between the pads 40b, 42b, 44b on the upper die 10 and the pads 40b, 42b, 44b on the lower die 12. As a result, the upper die 10 can respond to signals at times that are different from the times that the lower die 12 can respond to signals, which can produce undesired consequences.
There is therefore a need for an improved technique for separately routing signals to and/or from stacked integrated circuit dies.